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general description the max5858a evaluation kit (ev kit) is a fully assembled and tested circuit board that contains all the components necessary for evaluating the max5858a. the max5858a is a dual,10-bit, 300msps digital-to-analog converter (dac) with 4x/2x/1x-configurable interpolation filters. the max5858a also features a phase-locked-loop (pll) clock multiplier that generates and distributes all internally syn- chronized high-speed clock signals required by the input data latches, interpolation filters, and dac cores. the ev kit requires cmos-compatible data and clock inputs, and three separate 3v power supplies. the max5858a ev kit can also evaluate the max5858 (no pll) and the 8-bit max5856a (with pll). features ? allows fast evaluation and performance testing ? 3v and 2v cmos logic-level-compatible inputs ? also evaluates max5858/max5856a (with ic replacement) ? configurable, integrated 4x or 2x interpolation filters ? interleaved data mode ? on-board differential to single-ended output conversion circuitry ? sma coaxial connectors for clock inputs and dac outputs ? fully assembled and tested evaluates: max5858a/max5858/max5856a max5858a evaluation kit ________________________________________________________________ maxim integrated products 1 19-3182; rev 0; 12/03 component list for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range ic package MAX5858AEVKIT 0 c to +70 c 48 tqfp-ep* * ep = exposed pad. designation qty description c1, c2, c9, c10, c15, c16 6 10? 20%, 6.3v tantalum electrolytic capacitors (panasonic y case or avx a case) panasonic ecst0jy106r c3, c4, c11, c12, c17, c18 6 1? 10%, 10v x5r ceramic capacitors (0603) tdk c1608x5r1a105k c5, c22, c24, c25, c28 5 0.1? 10%, 25v x7r ceramic capacitors (0603) tdk c1608x7r1e104k c6, c7, c8, c19 4 0.1? 10%, 6.3v x5r ceramic capacitors (0201) tdk c0603x5r0j104k c13, c14 2 0.1? 10%, 10v x5r ceramic capacitors (0402) tdk c1005x5r1a104k c21, c23 2 5pf 0.25pf, 50v c0g ceramic capacitors (0603) tdk c1608c0g1h050c designation qty description c29 1 100pf 10%, 50v c0g ceramic capacitor (0603) tdk c1608c0g1h101k clk1, clkin, clkout, outa, outb 5 edge-mount sma connectors j1 1 21 x 2-pin header ju1?u11 11 2-pin headers l1, l2, l3 3 ferrite bead, 91 ? at 100mhz (1806) panasonic exc-ml45a910h r1, r6 0 not istalled resistor (0603) r2, r3, r4, r27 4 1k ? 5% resistors (0603) r5, r16, r18?21, r23 7 49.9 ? 1% resistors (0603) r17, r22 2 100 ? 1% resistors (0603) r24, r25 2 24.9 ? 1% resistors (0603) r26, r29, r30 3 10k ? 5% resistors (0603) r28 1 4.12k ? 1% resistor (0603) r31 1 1.91k ? 1% resistor (0805)
evaluates: max5858a/max5858/max5856a max5858a evaluation kit 2 _______________________________________________________________________________________ component suppliers supplier phone fax website coilcraft 847-639-6400 847-639-1469 www.coilcraft.com panasonic 714-373-7366 714-737-7323 www.panasonic.com tdk 847-803-6100 847-390-4405 www.component.tdk.com texas instruments 972-644-5580 214-480-7800 www.ti.com note: please indicate that you are using the max5858a when contacting these component suppliers. quick start (pll disabled) note: to evaluate pll-enabled mode, see the quick start (pll enabled) section. recommended equipment dc power supplies: digital 3v, 500ma analog 3v, 100ma clock 3v, 200ma two rf signal generators with low phase noise and low jitter for the clock input (e.g., hp 8662a) data generator (e.g., sony/tektronix dg2020a) two variable output pods (e.g., sony/tektronix p3420) spectrum analyzer oscilloscope digital voltmeter the max5858a ev kit is a fully assembled and tested surface-mount board. follow the steps below for board operation. do not turn on power supplies or enable signal generators until all connections are completed (figure 1): 1) verify that no shunt is installed across jumper ju1 (the clkin sma connector on the ev kit is not used for evaluating the max5858a in pll disabled mode). 2) verify that a shunt is installed across jumper ju2 (no dc offset at single-ended analog outputs outa and outb). 3) verify that a shunt is installed across jumper ju3 (ide disabled). 4) verify that a shunt is installed across jumper ju4 (pll disabled). 5) verify that a shunt is installed across jumper ju5 ( ren enabled, internal reference enabled). 6) verify that shunts are installed across jumpers ju6?u9 (differential output mode). 7) verify that no shunts are installed across jumpers ju10 and ju11. (clkxp and clkxn are used for evaluating the max5858a in pll disabled mode). 8) connect the rf output of the master hp 8662a (data clock) to the clock input on the back side of the data generator (sony/tektronix dg2020a). (see figure 1 for the equipment setup connections.) component list (continued) designation qty description t1, t3, t5, t6 4 transformers coilcraft z9370-b t2, t4 2 transformers coilcraft z9301-b u1 1 max5858aecm (48-pin tqfp?p) designation qty description u2 1 quadruple bus buffer gate with tri-state outputs ( 14- p i n ts s o p - p w) texas instruments sn74alvc125pwr none 11 shunts (ju1, ju10, ju11 any one pin), (ju2?u9 pins 1-2) none 1 max5858a pc board
9) connect the rf output of slave hp 8662a (ev kit clock) to the clkd sma connector on the ev kit. 10) synchronize master hp 8662a to the slave hp 8662a on the back side by connecting the int of the master to the ext of the slave generator. 11) verify that the data generator is programmed for cmos-level outputs, which transition from 0 to 3v. 12) connect data generator pod a to the first variable output pod (1). connect output channels ch9 through ch0 of variable output pod 1 to the max5858a ev kit connector j1, as indicated in table 1. 13) connect data generator pod b to the second vari- able output pod (2). connect output channels ch9 through ch0 of the variable output pod 2 to max5858a ev kit connector j1, as indicated in table 2. 14) connect the spectrum analyzer to the outa or the outb sma connector. 15) connect the 3v, 500ma power supply to dvdd. connect the ground terminal of this supply to dgnd. 16) connect the 3v, 100ma power supply to avdd. connect the ground terminal of this supply to agnd. 17) connect the 3v, 200ma power supply to pvdd. connect the ground terminal of this supply to pgnd. 18) turn on all three power supplies. 19) with a voltmeter, verify that 1.24v is measured at the refo pad on the ev kit. 20) enable the signal generators and the data generator. set both hp 8662as for an output amplitude of 2v p-p and identical frequencies (f clk ) of 165mhz. 21) adjust the phase of the master hp 8662a rf source, to meet the max5858a data timing specifications. 22) use the spectrum analyzer to view the max5858a output spectrum, or view the output waveforms using an oscilloscope on the outputs. evaluates: max5858a/max5858/max5856a max5858a evaluation kit _______________________________________________________________________________________ 3 variable pod 2 ch11 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 max5858a pin name cw db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 max5858a ev kit j1-1 j1-21 j1-19 j1-17 j1-15 j1-13 j1-11 j1-9 j1-7 j1-5 j1-3 variable pod 1 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 max5858a pin name da9/pd da8/ dacen da7/ f2en da6/ f1en da5/g3 da4/g2 da3/g1 da2/g0 da1 da0 max5858a ev kit j1-41 j1-39 j1-37 j1-35 j1-33 j1-31 j1-29 j1-27 j1-25 j1-23 master hp 8662a int* rf output slave hp 8662a ext* rf output max5858a ev kit clkd j1 10 11 pod a* pod b* clock input* *these connectors are located on the back side of the equipment. (da0?a9) (db0?b9, cw) dg2020a v ariable output pod 1 v ariable output pod 2 figure 1. max5858a ev kit quick start setup for pll disabled mode table 1. connector j1 table 2. connector j1
evaluates: max5858a/max5858/max5856a max5858a evaluation kit 4 _______________________________________________________________________________________ detailed description the max5858a ev kit is designed to simplify the evalu- ation of the max5858a 10-bit, dual, 300msps dac with pll. the board contains all circuitry necessary to eval- uate the dynamic performance of this high-speed con- verter, including circuitry to convert the dac? differen- tial output into a single-ended output. the ev kit provides pc board connector pads for power supplies avddin, dvddin, and pvddin. sma connectors are included for clock functions clkin, clkout, clkd, and dac outputs outa and outb connections. the four-layer pc board is a high-speed design that optimizes the dynamic performance of the dac by separating the analog and digital circuitry, which implements impedance matching for the differ- ential output signal pc board traces. the pc board traces have been designed for 50 ? impedance. power supplies the max5858a ev kit requires separate analog, digital, and pll power supplies. connect a 3v power supply to the avddin pc board pad to power the analog portion of the dac. connect the second 3v power supply to the dvddin pc board pad to power the digital portion of the dac. connect the third 3v power supply to the pvd- din pc board pad to power the pll portion of the dac. digital inputs the max5858a ev kit provides connector j1 for the two 10-bit input data buses. data bits da9 through da2 of channel a share a dual function for data and control word. the control word is latched by the cw bit (j1-1). the control word is latched on the falling edge of cw . refer to the max5858a data sheet for a detailed description of the control and data word functions. the data word is latched on the rising edge of the clk out- put, pin 20 of the max5858a. dac output the max5858a ev kit is designed to provide two pairs of analog outputs. the outputs can be configured for either differential or single-ended mode of operation. in differential mode and with transformer-coupled output and 50 ? external termination, the max5858a delivers a -2dbm output signal. in single-ended mode, the output amplitude is 1v p-p at both positive and negative dac outputs. to configure the max5858a for single-ended output operation, remove jumpers ju6?u9, and mea- sure the outputs at the a+, a-, and b+, b- 2-pin head- ers. to configure the max5858a for differential output operation, install shunts on jumpers ju6?u9, and measure the outputs at the outa and outb sma con- nectors. table 3 lists the jumper configuration for the dac output mode selection. output dc offset the max5858a ev kit features an option to add a dc offset to the analog output signals. to add a dc offset, remove jumper ju2 and connect an appropriate dc source across jumper ju2. the dc source has to be able to sink at least 40ma of dc current. the dc offset must be within 0 to 1.25v. interleaved data mode the max5858a, max5858, and max5856a feature an interleaved data mode that multiplexes the data inputs of both channels through port a. this feature allows the user to reduce the bit width of the input data bus. in interleaved data mode, channel b data is latched on the falling edge of the clock (clk), and channel a data is latched on the following rising edge of the clock (clk). jumper ju3 sets the interleaved data mode option. table 4 lists the jumper selection. shunts position dac output mode analog output locations installed differential mode outa and outb sma connectors not installed single-ended mode a+, a- and b+, b- 2-pin headers table 3. dac output mode (jumpers ju6?ju9) shunt position max5858a ide pin interleaved data mode not installed connected to dvdd with r26 enabled installed connected to dgnd disabled table 4. interleaved data mode (jumper ju3) shunt position max5858a ren pin reference voltage option not installed connected to avdd with r30 external reference installed connected to agnd internal reference table 5. reference voltage option (jumper ju5)
evaluates: max5858a/max5858/max5856a max5858a evaluation kit _______________________________________________________________________________________ 5 reference voltage options the max5858a ev kit supports both internal and exter- nal reference configurations. the internal reference voltage can be accessed at the refo pad. the ev kit also accepts an external reference voltage at the refo pad to set the full-scale analog-output signal level. jumper ju5 selects the reference voltage options for the ev kit. table 5 lists the jumper selection. evaluating the max5858 the max5858a ev kit also evaluates the pin-compatible max5858. refer to the max5858 data sheet for more details on the max5858 functions. to evaluate the max5858, replace u1 with the max5858 and install a shunt on jumper ju4. evaluating the max5856a the max5858a ev kit also evaluates the max5856a. refer to the max5856a data sheet for more details on the max5856a functions. to evaluate the max5856a, the following component changes on the max5858a ev kit are necessary: replace u1 with the max5856a. install a shunt on j1-3 and j1-4. install a shunt on j1-5 and j1-6. install a shunt on j1-23 and j1-24. install a shunt on j1-25 and j1-26. see tables 6 and 7 for the data bits of the max5856a, with respect to header j1 on the max5858a ev kit. pll clock multiplier (max5858a and max5856a only) the max5858a (10 bit) and max5856a (8 bit) feature a pll clock multiplier that generates and distributes all internally synchronized high-speed clock signals required by the input data latches, interpolation filters, and dac cores. jumper ju4 sets the pll clock multi- plier options. table 8 lists the jumper selection. clock the max5858a ev kit features two input clock options: a single-ended input clock applied to clkin or a differen- tial clock applied to clkd. when evaluating the max5858a or the max5856a, clkin is used in pll enabled mode, and clkd is used in pll disabled mode. the clock signal applied to the clkin sma input connector has to meet cmos logic-level requirements. when evaluating the max5858, only the clkd sma input connector is used. jumpers ju1, ju4, ju10, and ju11 set the input clock mode for the max5858a. table 9 lists the jumper configurations. table 6. max5856a data bits da7 through da0 on the max5858a ev kit table 8. pll clock multiplier (jumper ju4) for max5858a and max5856a clock mode jumper settings clkin mode max5858a or max5856a pll enabled; ju1, ju10, and ju11 installed; ju4 not installed clkd mode max5858 or max5858a, or max5856a pll disabled; ju1, ju10, and ju11 not installed; ju4 installed table 9. input clock selection max5856a pin name da7/pd da6/ dacen da5/ f2en da4/ f1en da3/g3 da2/g2 da1/g1 da0/g0 short to dgnd short to dgnd max5858a ev kit j1-41 j1-39 j1-37 j1-35 j1-33 j1-31 j1-29 j1-27 j1-25 j1-23 table 7. max5856a data bits db7 through db0 on the max5858a ev kit max5856a pin name db7 db6 db5 db4 db3 db2 db1 db0 short to dgnd short to dgnd cw max5858a ev kit j1-21 j1-19 j1-17 j1-15 j1-13 j1-11 j1-9 j1-7 j1-5 j1-3 j1-1 shunt position pllen pin pll clock multiplier not installed connected to pvdd with r29 enabled installed connected to pgnd disabled
evaluates: max5858a/max5858/max5856a quick start (pll enabled) recommended equipment dc power supplies: digital 3v, 500ma analog 3v, 100ma clock 3v, 200ma pulse generator for the clock inputs (e.g., hp 8131a) data generator (e.g., sony/tektronix dg2020a) two variable-output pods (e.g., sony/tektronix p3420) spectrum analyzer oscilloscope digital voltmeter do not turn on power supplies or enable signal gener- ators until all connections are completed (figure 2): 1) verify that a shunt is installed across jumper ju1. (clkin sma connector on the ev kit is used for evaluating the max5858a in pll enabled mode). 2) verify that a shunt is installed across jumper ju2 (no dc offset at the single-ended analog outputs outa and outb). 3) verify that a shunt is installed across jumper ju3 (ide disabled). 4) verify that no shunt is installed across jumper ju4 (pll enabled). 5) verify that a shunt is installed across jumper ju5 ( ren enabled, internal reference enabled). 6) verify that shunts are installed across jumpers ju6?u9 (differential output mode). max5858a evaluation kit 6 _______________________________________________________________________________________ variable pod 1 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 max5858a pin name da9/pd da8/ dacen da7/ f2en da6/ f1en da5/g3 da4/g2 da3/g1 da2/g0 da1 da0 max5856a pin name da7/pd da6/ dacen da5/ f2en da4/ f1en da3/g3 da2/g2 da1/g1 da0/g0 short to dgnd short to dgnd max5858a ev kit j1-41 j1-39 j1-37 j1-35 j1-33 j1-31 j1-29 j1-27 j1-25 j1-23 table 10. connector j1 table 11. connector j1 variable pod 2 ch11 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 max5858a pin name cw db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 max5856a pin name cw db7 db6 db5 db4 db3 db2 db1 db0 short to dgnd short to dgnd max5858a ev kit j1-1 j1-21 j1-19 j1-17 j1-15 j1-13 j1-11 j1-9 j1-7 j1-5 j1-3 must be able to adjust delay between trig output and output hp 8131a output trig output max5858a ev kit clkin j1 10 11 pod a* pod b* clock input* *these connectors are located on the back side of the equipment. (da0?a9) (db0?b9, cw) dg2020a v ariable output pod 1 v ariable output pod 2 figure 2. max5858a ev kit quick start setup for pll enabled mode
7) verify that shunts are installed across jumpers ju10 and ju11 (clkxp and clkxn are not used for evaluating the max5858a in pll enabled mode). 8) connect the trig output (clock synchronize sig- nal) of the hp 8131a to the clock input on the back side of the data generator (sony/tektronix dg2020a). (see figure 2 for the equipment setup connections.) 9) connect the output signal of the hp 8131a to the clkin sma connector on the ev kit. 10) verify that both the pulse generator and the data generator are programmed for cmos level outputs, which transition from 0 to 3v. 11) connect data generator pod a to the first variable output pod (1). connect output channels ch9 through ch0 of the variable output pod 1 to the max5858a ev kit connector j1, as indicated in table 10. 12) connect data generator pod b to the second vari- able output pod (2). connect output channels ch9 through ch0 of the variable output pod 2 to the max5858a ev kit connector j1, as indicated in table 11. 13) connect the spectrum analyzer to the outa or the outb sma connector. 14) connect the 3v, 500ma power supply to dvdd. connect the ground terminal of this supply to dgnd. 15) connect the 3v, 100ma power supply to avdd. connect the ground terminal of this supply to agnd. 16) connect the 3v, 200ma power supply to pvdd. connect the ground terminal of this supply to pgnd. 17) turn on all three power supplies. 18) with a voltmeter, verify that 1.24v is measured at the refo pad on the ev kit. 19) enable the pulse generator and the data generator. for 1x interpolation, set the hp 8131a output for a square wave with a frequency (f clk ) of 165mhz. for 2x interpolation, set the hp 8131a output for a square wave with a frequency (f clk ) of 150mhz. for 4x interpolation, set the hp 8131a output for a square wave with a frequency (f clk ) of 75mhz. 20) adjust the delay between the hp 8131a trig out- put and signal output to meet the max5858a data timing specifications. 21) use the spectrum analyzer to view the max5858a output spectrum, or view the output waveforms using an oscilloscope on the outputs. evaluates: max5858a/max5858/max5856a max5858a evaluation kit _______________________________________________________________________________________ 7
evaluates: max5858a/max5858/max5856a max5858a evaluation kit 8 _______________________________________________________________________________________ figure 3. max5858a ev kit schematic r6 open clkd j1-14 j1-10 j1-6 j1-18 j1-22 j1-26 j1-30 j1-42 j1-38 j1-34 r27 1k ? r26 10k ? r5 49.9 ? 1% r1 open r2 1k ? r3 1k ? j1-13 j1-9 j1-5 j1-17 j1-21 j1-25 j1-29 j1-41 j1-37 j1-33 header 21 12 j1 j1-16 j1-12 j1-8 j1-20 j1-24 j1-28 j1-32 j1-40 j1-36 j1-15 j1-11 j1-7 j1-19 j1-23 j1-27 j1-31 j1-39 j1-35 r24 24.9 ? 1% c22 0.1 f c24 0.1 f c25 0.1 f j1-2 dvdd j1-1 ju3 j1-4 j1-3 pvdd lock refo dvdd ju10 ju11 r4 1k ? r29 10k ? ju4 pvdd dvdd avdd av dd av dd pv dd dv dd dv dd dv dd clk dgnd 1 3 6 4 clkin clkout r30 10k ? ju5 avdd r31 1.91 ? 1% ju1 3 6 8 11 14 u2 12 9 5 2 4 10 1 13 7 1y 2y 3y 4y v cc 2oe 3oe 1oe 4oe 2a 3a 1a 4a 20 46 40 32 7 18 48 45 44 42 41 30 31 28 36 34 39 38 37 47 19 6 33 43 1 2 3 4 5 8 9 10 11 12 13 14 15 16 17 22 23 24 25 26 27 21 29 35 outpa outna outpb outnb clkxp clkxn lock refo pllf refr n.c. n.c. dgnd dgnd dgnd pgnd agnd clk da9/pd da8/dacen da7/f2en da6/f1en da5/g3 da4/g2 da3/g1 da2/g0 da1 da0 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 cw ide pllen ren gnd t1 r25 24.9 ? 1% 1 3 6 3 2 1 4 5 6 4 outa ju2 t3 t2 dvdd dvdd pvdd 1 3 6 3 2 1 4 5 6 4 outb t5 t6 t4 6 4 1 3 t6 c21 5pf r16 49.9 ? 1% r17 100 ? 1% r18 49.9 ? 1% r19 49.9 ? 1% agnd a+ ju6 ju7 agnd a- c23 5pf c28 0.1 f c8 0.1 f c7 0.1 f c6 0.1 f c13 0.1 f c5 0.1 f c2 10 f 6.3v c4 1 f c3 1 f c1 10 f 6.3v r20 49.9 ? 1% r22 100 ? 1% r23 49.9 ? 1% r21 49.9 ? 1% c29 100pf r28 4.12k ? 1% agnd b+ ju8 ju9 agnd b- u1 max5858a dvddin l1 dgnd pvdd c19 0.1 f c16 10 f 6.3v c18 1 f c17 1 f c15 10 f 6.3v pvddin l3 pgnd avdd c14 0.1 f c10 10 f 6.3v c12 1 f c11 1 f c9 10 f 6.3v avddin l2 agnd dgnd dgnd dgnd dgnd dgnd pgnd agnd common ground point dgnd agnd agnd pgnd pgnd agnd pgnd pgnd pgnd pgnd agnd agnd agnd agnd agnd
evaluates: max5858a/max5858/max5856a max5858a evaluation kit _______________________________________________________________________________________ 9 figure 4. max5858a ev kit component placement guide?omponent side
evaluates: max5858a/max5858/max5856a max5858a evaluation kit 10 ______________________________________________________________________________________ figure 5. max5858a ev kit pc board layout?omponent side
evaluates: max5858a/max5858/max5856a max5858a evaluation kit ______________________________________________________________________________________ 11 figure 6. max5858a ev kit pc board layout (inner layer 2)?round planes
evaluates: max5858a/max5858/max5856a max5858a evaluation kit 12 ______________________________________________________________________________________ figure 7. max5858a ev kit pc board layout (inner layer 3)?ower planes
evaluates: max5858a/max5858/max5856a max5858a evaluation kit ______________________________________________________________________________________ 13 figure 8. max5858a ev kit pc board layout?older side
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. evaluates: max5858a/max5858/max5856a max5858a evaluation kit figure 9. max5858a ev kit component placement guide?older side maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products.

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